Dr. Susan Schober profile photo

Dr. Susan Schober

Co-Founder

Los Angeles, CA, UNITED STATES

Dr. Schober is an inventor and entrepreneur with expertise in the area of electrical engineering and analog integrated circuit design.

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Biography

Susie is an inventor and entrepreneur with expertise in the area of electrical engineering, specifically analog integrated circuit design. She has experience from the start to finish of an IC including the specifications, design, layout, simulation, photolithography, fabrication, testing, and commercialization of radio-frequency, mixed signal, and analog circuits and systems. Her interests include creating novel low power, high performance analog circuits for nanoscale CMOS technologies and the automation of analog IC design.

Areas of Expertise

Complementary Current Field Effect Transistor (CiFET)Analog & Digital IC DesignIntegrated Circuit DesignCadencePCB DesignCMOS

Accomplishments

1ST Prize, Best Student Paper Award, IEEE VI LASCAS

2015

International Travel Grant Award, USC WiSE

2015

Scholar Travel Grant Award, USC Ming Hsieh Institute

2015

Conference Travel Grant Award, USC Department of Electrical Engineering-Electrophysics

2015

1ST Prize, Best Paper Award, USC-ISI Viterbi Graduate Student Symposium

2014

Graduate Research Assistantship, MOSIS

2014 - 2015

Graduate Research Assistantship, USC-ISI, National Semiconductor/Texas Instruments, DARPA, and NSF

2008 - 2013

Chair Doctoral Fellowship, USC Dept. of Electrical Engineering-Electrophysics

2006 - 2010

Viterbi Family Fund Engineering Scholarship, USC

2005 - 2006

1ST Prize, Senior VLSI Design Project Winner, USC EE477L

2005

Farr Engineering Scholarship, USC

2004 - 2005

SCion Scholarship, USC

2002 - 2005

Trojan Junior Auxiliary League Scholarship, USC

2002 - 2004

Marilyn Sion Environmental Awareness Scholarship

2002

OC Physics Student of the Year Award

2002

Education

University of Southern California

Doctor of Philosophy, Electrical Engineering

2015

University of Southern California

Master of Science, Biomedical Engineering

2014

University of Southern California

Master of Science, Engineering Management

2010

University of Southern California

Master of Science, Electrical Engineering

2007

University of Southern California

Bachelor of Science, Electrical Engineering

2006

Affiliations

  • USC Viterbi School of Engineering : Adjunct Lecturer
  • IEEE Student Member
  • Tau Beta Pi (TBP) Engineering Honor Society Member
  • Eta Kappa Nu (HKN) Electrical Engineering Honor Society Member
  • Alpha Omega Epsilon (AOE) Engineering Sorority Member
  • Society of Women Engineers (SWE) Member
  • USC Women in Science and Engineering (WiSE) Member

Languages

  • English
  • Farsi
  • French
  • Spanish

Patents

COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES AND AMPLIFIERS

WO2017019064

2017-02-02

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COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES AND AMPLIFIERS

US10211781

2019-02-19

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COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES AND AMPLIFIERS

EP3329598

2018-06-06

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COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES AND AMPLIFIERS

CA3031736

2017-02-02

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COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES AND AMPLIFIERS

CN10814121

2018-06-08

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COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES AND AMPLIFIERS

KR20180034555

2018-04-04

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SUPER-SATURATION CURRENT FIELD EFFECT TRANSISTOR AND TRANS-IMPEDANCE MOS DEVICE

WO2017105554

2017-06-22

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SUPER-SATURATION CURRENT FIELD EFFECT TRANSISTOR AND TRANS-IMPEDANCE MOS DEVICE

US10283506

2019-05-07

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SUPER-SATURATION CURRENT FIELD EFFECT TRANSISTOR AND TRANS-IMPEDANCE MOS DEVICE

CN108140613

2018-06-08

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MULTI-STAGE AND FEED FORWARD COMPENSATED COMPLEMENTARY CURRENT FIELD EFFECT TRANSISTOR AMPLIFIERS

WO2017019973

2017-02-02

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MULTI-STAGE AND FEED FORWARD COMPENSATED COMPLEMENTARY CURRENT FIELD EFFECT TRANSISTOR AMPLIFIERS

US20180226930

2018-08-09

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MULTI-STAGE AND FEED FORWARD COMPENSATED COMPLEMENTARY CURRENT FIELD EFFECT TRANSISTOR AMPLIFIERS

CN108141181

2018-06-08

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LOW NOISE TRANS-IMPEDANCE AMPLIFIERS BASED ON COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES

WO2017019978

2017-02-02

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LOW NOISE TRANS-IMPEDANCE AMPLIFIERS BASED ON COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES

US20180219519

2018-08-02

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LOW NOISE TRANS-IMPEDANCE AMPLIFIERS BASED ON COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES

CN108141180

2018-06-08

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REFERENCE GENERATOR AND CURRENT SOURCE TRANSISTOR BASED ON COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES

WO2017019981

2017-02-02

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REFERENCE GENERATOR AND CURRENT SOURCE TRANSISTOR BASED ON COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES

US20180224878

2018-08-09

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REFERENCE GENERATOR AND CURRENT SOURCE TRANSISTOR BASED ON COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES

CN108140614

2018-06-08

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SCALABLE INTEGRATED DATA CONVERTER

WO2017106835

2017-06-22

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SCALABLE INTEGRATED DATA CONVERTER

EP3391544

2018-10-24

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SCALABLE INTEGRATED DATA CONVERTER

CN108702155

2018-10-23

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SCALABLE INTEGRATED DATA CONVERTER

JP2019504585

2019-02-14

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LOW NOISE SENSOR AMPLIFIERS AND TRANS-IMPEDANCE AMPLIFIERS USING COMPLEMENTARY PAIR OF CURRENT INJECTION FIELD-EFFECT TRANSISTOR DEVICES

WO2018098389

2018-05-31

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PHASE FREQUENCY DETECTOR AND ACCURATE LOW JITTER HIGH FREQUENCY WIDE-BAND PHASE LOCK LOOP

WO2016118936

2016-07-28

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PHASE FREQUENCY DETECTOR AND ACCURATE LOW JITTER HIGH FREQUENCY WIDE-BAND PHASE LOCK LOOP

US20170373697

2017-12-28

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PHASE FREQUENCY DETECTOR AND ACCURATE LOW JITTER HIGH FREQUENCY WIDE-BAND PHASE LOCK LOOP

CA2973368

2016-07-28

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PASSIVE PHASED INJECTION LOCKED CIRCUIT

WO2016118183

2016-07-28

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PASSIVE PHASED INJECTION LOCKED CIRCUIT

US20180019757

2018-01-18

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PASSIVE PHASED INJECTION LOCKED CIRCUIT

CA2974821

2016-07-28

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TRACK AND HOLD CIRCUIT

WO2018200482

2018-12-06

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CHARGE-BASED PHASE LOCKED LOOP CHARGE PUMP

US8525564

2013-09-03

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ELASTOMERIC OPTICAL TACTILE SENSOR

WO2012129410

2012-12-27

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Selected Articles

A 1.25mW 0.8-28.2GHz Charge Pump PLL with 0.82ps RMS Jitter in All-Digital 40nm CMOS | International Symposium on Circuits and Systems (ISCAS 2015)

Susan Schober, John Choma

2015

This paper presents a wide-operating range analog phase locked loop (PLL) constructed from all-digital integrated circuit (IC) process components. Specifically, this work introduces 2 cutting-edge, scalable analog circuit designs for a charge pump (CP) and a voltage controlled oscillator (VCO). The ultra-low power and highly accurate CP circuit uses 6 minimum-sized transistors, a small metal interconnect capacitor, and, unlike the state-of-the-art, no current mirrors. The ring VCO has a reconfigurable, expandable structure and is capacitively tunable allowing for an exceptionally large frequency operating range of 0.8 to 28.2GHz making it suitable for variety of wireless and wireline applications. The PLL has been fabricated in a TSMC 40nm all-digital CMOS process and physically tested with a 0.5-1.2V supply. The fabricated PLL has an area of 0.0048mm 2 , consumes a maximum of 1.25mW, and has a 0.82 ±0.0275ps RMS jitter over the entire operating range.

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A Dual Reset D Flip-Flop Phase-Frequency Detector for Phase Locked Loops | Iberchip

Susan Schober, John Choma

2015

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A Charge Transfer-Based High Performance, Ultra-Low Power PLL Charge Pump | Latin American Symposium on Circuits and Systems (LASCAS 2015)

Susan Schober, John Choma

2015

This paper presents a high performance, ultra-low power scalable charge pump (CP) design for analog phase locked loops (PLLs). The compact CP circuit uses 4 minimum-sized transistor switches and a relatively small capacitor for transferring charge within the PLL to adjust the voltage controlled oscillator (VCO) frequency. Unlike the state of the art, the proposed CP design does not use current mirrors, has the ability to operate at very low voltages, and does not suffer from traditional mismatch errors due to its unique design. The fast switching action of the proposed CP allows for the use of a no-added delay D-flip flop (DFF) based phase-frequency detector (PFD) resulting in reduced PLL control loop delay and very low reference spurs in a PLL design. The proposed CP has been fabricated with a 1-10GHz PLL in TSMC all-digital 40nm CMOS process and physically tested with a variable 0.5-1.2V supply and a 50MHz-1GHz reference frequency. The charge pump has an active area of 0.0004mm 2 , consumes on average 250pW power, and has a 0.1-0.3° phase error, depending on the PLL frequency of operation.

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Drug Delivery Using Wireless MEMS | Handbook of MEMS for wireless and mobile applications

Roya Sheybani, Susan M. Schober, Ellis Meng

2013

Drug delivery is essential for the treatment of chronic conditions. Implantable site-specific drug delivery devices offer direct delivery to the site of therapy, improving treatment outcomes while reducing side effects and overall associated healthcare costs. Microelectromechanical systems (MEMS) miniaturize infusion pumps such that they are implantable; wirelessly-powered to eliminate the use of bulky, limited lifetime batteries; and volume efficient. Wireless communication allows remote monitoring of device status and performance, and remotely initiated changes to the drug regimen for patient tailored therapy. Requirements for a MEMS drug delivery device with wireless powering and data communication are presented along with an example of such a device.

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A Capacitively Phase-Coupled Low Noise, Low Power 0.8-to-28.2GHz Quadrature Ring VCO in 40nm CMOS | New Circuits and Systems Conference (NEWCAS 2015)

Susan Schober, John Choma

2015

This paper presents a novel tunable wide-operating range capacitively phase-coupled low noise, low power ring-based voltage controlled oscillator (VCO) for use in multi-GHz phase-locked loops (PLLs). The basic building blocks of the ring oscillator (RO) design are discussed along with a technique to expand the VCO to a variety of phases and frequencies without the use of physical inductors. Improved performance with minimal phase noise are achieved in this ring VCO design through distributed passive-element injection locking (IL) of the staged phases via a network of symmetrically placed metal interconnect capacitors. Using this method, a 0.8-to-28.2 GHz quadrature ring VCO was designed, fabricated, and physically tested with a PLL in an all-digital 40nm TSMC CMOS process. Most notably the proposed quadrature VCO occupies an area of 0.0024mm2, consumes a power of 0.88mW at a 1.0V supply voltage, and possesses a phase noise of -124.5dBc/Hz at the 10MHz offset for a carrier frequency of 28.0GHz.

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